Digital IC Design - Lab 7 - ECE 421L

Author: Brian Wolak,

Email: wolak@unlv.nevada.edu

October 20th, 2021

Lab Description

- This lab will focus on the design, layout and simulation of various logic components using buses and arrays. All designs and implementations will be performed using the ONSEMI C5 process. 

Pre-Laboratory Procedure

- All previous work was backed up using .zip files and my personal Google Drive prior to beginning this lab

- Tutorial 5 was completed and lab documentation was reviewed in its entirety in preparation for this lab

Laboratory Objectives

1.) Design a 4-bit word inverter schematic and simulate using the following conditions listed below

- out<3> is connected to a 100fF, out<2> is connected to a 500fF capacative load

- out<1> is connected to a 1pF capactive load, and out<0> is not connected to any load

2.) Design schematics and symbols for an 8 bit in/out array of NAND, NOR, AND, inverter, and OR gates

- provide a few simulations of each

3.) Design a schematic and symbol for a 2:1 MUX/DEMUX device 

- explain using simulations how the device operates and can be used for each instance

4.) Design a schematic and simulate an 8-bit word 2:1 MUX/DEMUX device schematic and symbol

- be sure the device only has one select input through the use of an inverter

5.) Draft the full-adder circuit seen in Fig. 12.20 of the CMOS 4th Edition textbook using 6u/600n devices 

- create a symbol for the device and then use this symbol to create an 8-bit adder schematic and symbol

- simulate the 8-bit adder device to prove its operation

6.) Lay out the 8-bit adder cell showing DRC and LVS confirmation

Laboratory Procedure

4-bit Word Inverter

I'll begin by creating a sinmple inverter and then use that device design to create a 4-bit word inverter through the use of arrays. The inverter will then be simulated to show proper operation and fuinctionality.

Figures 1-2: single bit inverter schematic and symbol

Figure 3: 4-bit inverter schematic created using device instantiation

Figure 4: 4-bit inverter symbol 

Figure 5: 4-bit inverter simulation schematic using the symbol view created above

Figure 6: 4-bit inverter simulation results using Cadence Spectre simulator

NOTE: reviewing the simulation results we can clearly see the higher capacitance causes a slower rise and fall time in each bit connected to the output when compared to the '0' bit which was left with zero capactitance on the output.

8-bit Static Logic Gates

Moving onto the 8-bit logic gates, I will begin with a simple schematic of each gate, then use that schematic to create a symbol view. Once the symbol view is created for a simgle bit, I will then use the singel bit device to instantiate a 8-bit device and symbol view. The devices will then all be combined into a large simulation to display proper logical operations.

NOT Gate

Figure 7-8: single bit inverter with symbol view

Figure 9: 8-bit inverter schematic

Figure 10: 8-bit inverter symbol

NAND Gate

Figure 11-12: single bit NAND gate schematic and symbol

Figure 13: 8-bit NAND schematic

Figure 14: 8-bit NAND symbol view

NOR Gate

Figure 15-16: single bit NOR gate schematic and symbol view

Figure 17: 8-bit NOR gate schematic 

Figure 18: 8-bit NOR gate symbol view

AND Gate

Figure 19-20: single bit AND gate schematic and symbol view

Figure 21: 8-bit AND gate schematic

Figure 22: 8-bit AND gate symbol view

OR Gate

Figure 23-24: single bit OR gate schematic and symbol view

Figure 25: 8-bit OR gate schematic

Figure 26: 8-bit OR gate symbol view

XOR Gate 

Figure 27-28: single bit XOR gate schematic with symbol view

Figure 29: 8-bit XOR gate schematic 

Figure 30: 8-bit XOR symbol view

Logic Gate Simulation

Figure 31: 8-bit logic gate simulation circuit

Figure 32: 8-bit logic simulation results using Cadence Spectre showing preop logical operation for all gates

2:1 MUX/DEMUX

Figure 33: 2:1 multiplexer schematic

Figure 34: 2:1 multiplexer symbol view

Figure 35: 8-bit multiplexer schematic

NOTE: because we have only two inputs (or outputs when used as a DEMUX) I implemented an inverter to simplify the select circuit and allow a single input to selct the input or output of the device. If this was a larger device, it would require more than one single input select signal.

Figure 36: 8-bit multiplexer symbol view

Figure 37: 8-bit multixplexr simulation circuit showing MUX and DEMUX device capabilities

Figure 38: 8-bit MUX/DEMUX results showing proper operation of device properties

NOTE: when reviewing this simulation you can see that while the MUX select input is set to '1', the output recieves the 'A' input signal, and when the input switches to '0' or 'low', the output follows the 'B' input signal. Reviewing the DEMUX results you can see as well while the input select is '1' the 'DEMUXA' output recieves the output wave, and near the 100n area when it switches to '0' the 'DEMUXB' output folows the signal. This device can be used to seperate an input singal to two individual outputs while used in DEMUX, or accept two different inputs (individually) when used as a MUX device. One thing to note is that when the device switched during teh 0-1 transition the output of 'DEMUXA' remained high, this could eb fixed with the addition of a bleed off transistor which would drag the output low once the selection to the other output was made.

AOI Full Adder Device

Figure 39: AOI full-adder circuit in CMOS topology from Fig. 12.20 of the course textbook

Figure 40: AOI full-adder symbol view

Figure 41: 8-bit AOI full-adder schematic

Figure 42: 8-bit AOI full-adder symbol view

Figure 43: 8-bit AOI full-adder simulation circuit

Figure 44: 8-bit AOI full-adder simulation results performed using the Cadence Spectre Simulator

NOTE: in the simulation above two binary numbers were added using no carry input, and gave a correct output response.

A = 01111000 (decimal 120) 

B = 00101101 (decimal 45)

Sum = 10100101 (decimal 165)

Figure 45: single bit AOI full-adder layout

Figure 46: AOI single but extracted view

Figure 47: AOI single bit DRC confirmation

Figure 48: AOI single bit LVS confirmation

8-bit AOI Full-Adder Layout

Because of the extremly large size of the 8-bit AOI full-adder I will not be posting a full size layout image but rather a zoomed image of the LSB side and MSB side to show details of the input and output terminals using metal 3 as well as a 50/50 split of the extracted view.

Figure 49: 8-bit AOI full adder MSB shwoing bits 7 and 6

Figure 50: 8-bit AOI full-adder LSB showing 0 bit and carry input

Figure 51: 8-bit AOI full-adder 50/50 extracted view

Figure 52: 8-bit AOI ful-adder DRC and LVS confirmation

All design work for this lab including schematics, layouts and assocaited symbols with simulation files can be found here

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